The present invention relates to a Delay Locked Loop (DLL) for use in various systems which operate based on clocks, and more particularly, to a technology which enables DLL to operate at quick speed by employing a burst scheme.
Conventionally, a clock is used as a reference for regulating operation timing in systems or circuits, and is also used to ensure faster operation without an error. When a clock is provided from outside and used within a system or circuit, a time delay (also called “skew”) occurs due to internal circuits. To compensate such a time delay and make it sure that a phase of an internal clock is consistent with that of an external clock, DLL may be used.
Meanwhile, the DLL is less influenced by noises compared with a Phase Locked Loop (PLL) that is previously used and thus has been widely used in the field of synchronous semiconductor memories, including Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR SDRAM).
FIG. 1 is a block diagram showing a configuration of a conventional DLL.
Referring to FIG. 1, the conventional DLL includes a phase detector 110, a delay unit 120, and a replica delay unit 130.
The replica delay unit 130 delays an output clock OUTCLK of the DLL to generate a feedback clock FBCLK. This replica delay unit 130 has a delay amount that is derived by modeling delay elements through which the output clock OUTCLK is generated from the DLL and sent to a chip or system.
The phase detector 110 compares a phase of the input clock REFCLK (in general, a clock inputted from the outside of a chip (or system) to the DLL with that of the feedback clock FBCLK to output an up signal UP or down signal DN. If a phase of the input clock REFCLK precedes that of the feedback signal FBCLK, the phase detector 110 activates and outputs a down signal DN; and if a phase of the feedback signal FBCLK precedes that of the input clock REFCLK, it activates and outputs an up signal UP.
The delay unit 120 delays the input clock REFCLK to generate an output clock OUTCLK. A delay amount of the delay unit 120 is determined based on the up signal UP and the down signal DN, and increases whenever the up signal UP is activated and decreases whenever the down signal DN is activated.
Through this operation, the DLL generates its output clock OUTCLK to make sure that a rising edge of the feedback clock FBCLK can be consistent with that of the input clock REFCLk.
FIG. 2 shows a detailed circuit diagram of the delay unit 120 of FIG. 1.
As shown therein, the delay unit 120 is composed of a plurality of unit delay stages UD_1 to UD_N and a shift register 210.
The unit delay stages UD_1 to UD_N are used for delaying an input clock REFCLK to generate an output clock OUTCLK, in which the number of unit delay stages used is determined depending on output signals REG_1 to REG_N to be provided by the shift register 210. The input clock REFCLK is delayed through one of the unit delay stages UD_1 to UD_N that receives an activated one of the output signals REG_1 to REG_N and through the subsequent delay stages. For example, when the REG_3 is activated, the input clock REFCLK is delayed by the unit delay stages UD_3 to UD_N; and when the REG_4 is activated, the input clock REFCLK is delayed by the unit delay stages UD_4 to UD_N.
The shift register 210 activates one of its output signals REG_1 to REG_N in response to the up signal UP and the down signal DN. Whenever the up signal UP is activated, the shift register 210 activates the immediately adjacent one of the output signals REG_1 to REG_N on the left side of the currently activated output signal, and whenever the down signal DN is activated, the shift register 210 activates the immediately adjacent one of the output signals REG_1 to REG_N on the right side one of the currently activated output signal, wherein the order of the output signals from left to right matches the order of the unit delay stages from left to right in series. For example, in a state where REG_3 is activated, when the up signal UP is activated once, REG_2 is activated; and in a state where REG_3 is activated, when the down signal DN is activated once, REG_4 is activated. Therefore, whenever the up signal UP is activated, a delay amount of the delay unit 120 increases by one unit delay of the unit delay stages UD_1 to UD_N; and whenever the up signal UP is activated, a delay amount of the delay unit 120 decreases by one unit delay of the unit delay stages UD_1 to UD_N.
The DLL operates in a certain periodic cycle. This is because the DLL performs the process as follows: a relative phase between the input clock REFCLK and the feedback clock FBCLK is detected by the phase detector 110, the result is provided as a feedback to the delay unit 120 to be reflected thereat, and the output clock OUTCLK of the delay unit 120 is delayed by the replica delay unit 130. According to the conventional DLL, however, a delay value is varied by a unit delay amount per each cycle (that is, a delay value per each cycle is varied only by one unit delay step). Thus, this method makes a locking time (which is time taken until a rising edge of the feedback clock FBCLK becomes consistent with that of the input clock REFCLK) of DLL considerably longer. Even after locking, time taken to again correct a phase of clock (REFCLK, FBCLK, or OUTCLK), if any of them varies, may be prolonged. Since these factors are directly related to the performance of DLL, there is a need for a technology that allows the DLL to relatively rapidly operate.